The present invention relates generally to the field of integrated circuits, and more particularly, to a wafer-interposer assembly apparatus and method.
Semiconductor die have traditionally been electrically connected to a package by wire bonding techniques, in which wires are attached to pads of the die and to pads located in the cavity of the plastic or ceramic package. Wire bonding is still the interconnection strategy most often used in the semiconductor industry today. But the growing demand for products that are smaller, faster, less expensive, more reliable and have a reduced thermal profile has pushed wire bonding technology to its limits (and beyond) thereby creating barriers to sustained product improvement and growth.
The high-performance alternative to wire bonding techniques are flip chip techniques, in which solder balls or bumps are attached to the input/output (I/O) pads of the die at the wafer level. The bumped die is flipped over and attached to a substrate xe2x80x9cface down,xe2x80x9d rather than xe2x80x9cface upxe2x80x9d as with wire bonding. Flip chips resolve many if not all of the problems introduced by wire bonding. First, flip chips have fewer electrical interconnects than wire bonding, which results in improved reliability and fewer manufacturing steps, thereby reducing production costs. Second, the face down mounting of a flip chip die on a substrate allows superior thermal management techniques to be deployed than those available in wire bonding. Third, flip chips allow I/O to be located essentially anywhere on the die, within the limits of substrate pitch technology and manufacturing equipment, instead of forcing I/O to the peripheral of the die as in wire bonding. This results in increased I/O density and system miniaturization.
Despite the advantages of the flip chip, wide spread commercial acceptance of the flip chip has been hindered by testing issues. To ensure proper performance, the die should be adequately tested before it is assembled into a product; otherwise, manufacturing yields at the module and system level can suffer and be unacceptably low. Under some circumstances, a defective die can force an entire subassembly to be scrapped. One attempt to address this testing issue has been to perform a wafer probe, followed by dicing the wafer and temporarily packaging each die into a test fixture of some sort. Performance testing is subsequently executed. Burn-in testing is often included in this process to eliminate any die having manufacturing process defects. Following the successful completion of these tests, the die are removed from the test fixture and either retailed as a Known Good Die (xe2x80x9cKGDxe2x80x9d) product or used by the manufacturer in an end product, such as a Multichip Module (xe2x80x9cMCMxe2x80x9d). The Multichip Module may constitute a subassembly in a larger system product. This Known Good Die process is inherently inefficient due to its complexity.
Accordingly, there is a need for a wafer-interposer assembly apparatus and method that is simple, allows testing at the wafer level before dicing, and eliminates the need for temporarily packaging the die in a carrier.
The present invention provides a wafer-interposer assembly apparatus and method that is simple, allows testing at the wafer level before dicing, and eliminates the need for temporarily packaging the die in a carrier. As a result, the number of manufacturing operations are reduced, thereby improving first pass yields. In addition, manufacturing time is decreased, thereby improving cycle times and avoiding additional costs.
More specifically, the present invention provides several possible test systems, apparatus and method of interfacing multiple semiconductor wafer to the testing equipment through the use of interposer assemblies, which enhances economies of scale. The interposer revolutionizes the semiconductor fabrication process enabling testing and burn-in of all die at the wafer level. For example, the interposer eliminates the need to singulate, package, test, then unpackage each die individually to arrive at a Known Good Die product stage. Furthermore, the interposer may remain attached to the die following dicing, thereby providing the additional benefit of redistributing the die I/O pads to a standard Joint Electrical Dimensional Electronic Commnittee (xe2x80x9cJDECxe2x80x9d) interconnect pattern for Direct Chip Attachment (xe2x80x9cDCAxe2x80x9d) applications.
The present invention provides a method for manufacturing a wafer-interposer assembly including the steps of providing a semiconductor wafer and an interposer. The semiconductor wafer including one or more semiconductor die, each semiconductor die having one or more first electrical contact pads. The interposer having one or more communication interfaces and a second electrical contact pad corresponding to each of the one or more first electrical contact pads on each semiconductor die of the semiconductor wafer, and at least one of the second electrical contact pads electrically connected to the one or more communication interfaces. The wafer-interposer assembly is formed by connecting each first electrical contact pad of the semiconductor wafer to the corresponding second electrical contact pad of the interposer with a conductive attachment element.
The present invention also provides a wafer-interposer assembly having an interposer connected to a semiconductor wafer. The semiconductor wafer includes one or more semiconductor die, each semiconductor die having one or more first electrical contact pads. The interposer includes one or more communication interfaces and a second electrical contact pad corresponding to each of the one or more first electrical contact pads on each semiconductor die of the semiconductor wafer, at least one of the second electrical contact pads electrically connected to the one or more communication interfaces, and each first electrical contact pad of the semiconductor wafer connected to the corresponding second electrical contact pad of the interposer with a conductive attachment element.
In addition, the present invention provides an interposer having a multi-layer sheet having a first surface and a second surface, a first pattern of electrical contact pads disposed on the first surface, one or more communication interfaces and a set of conductors. The first pattern of electrical contact pads correspond to a second pattern of electrical contact pads disposed on a surface of a semiconductor wafer. The one or more communication interfaces are attached to the multi-layer sheet. The set of conductors each of which connect at least one electrical contact pad disposed on the first surface to the one more communication interfaces.
Moreover, the present invention provides wafer-interposer assemblies having various types of communication interfaces, such as integral edge connector(s) with pins and/or sockets, integral bayonet connector(s) with pins and/or sockets, one or more connectors added to the wafer-interposer assembly, one or more soldered connections, one or more ribbon connectors, one or more RF connectors, one or more optical or infrared connectors, one or more transmit/receive antennas, or one or more clamps or quick release devices.
Other features and advantages of the present invention shall be apparent to those of ordinary skill in the art upon reference to the following detailed description taken in conjunction with the accompanying drawings.